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THNCFxxxMAA Series
Product Specifications Dimensions Dimensions Type I card Weight
Preliminary version
36.4mm(L) x 42.8mm (W) x 3.3mm (H) 14.2 g or 0.5 oz
Capacities Storage Capacities
8,16, 32, 48, 64, 96, 128, 160, 192, 256, 320, 384 and up to 512 MB Mbytes (unformatted)
Compatibility System Compatibility Please refer to the compatibility list. Performance Performance Data Transfer Rates: To/from Flash memory: To/from host: Sustained write: Sustained read: Command to DREQ: Idle to Read Idle to Write SRAM data buffer
up to 4.1Mbyte/s in ATA PIO mode 4 up to 12.5 Mbytes/s up to 20Mbytes/s up to 2.98Mbyte/s in ATA PIO mode 4 up to 5.62Mbyte/s in ATA PIO mode 4 <4ms <1 s <1 s 6 KBytes SRAM
Voltage Operating Voltage
3.3V / 5V +/- 10%
consumption Power consumption Read mode 30 mA (typ) Write mode 30 mA (typ) Sleep mode 100uA (typ) conditions Environment conditions Operating temperature Storage temperature Relative humidity
0 to 60 -20 to 65 95%(Max)
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THNCFxxxMAA Series
Electrical Specification
Preliminary version
ABSOLUTE MAXIMUM RATINGS
SYMBOL Vcc Vin Tstg Topr RATING Power Supply Voltage Input Voltage Storage Temperature Operating Temperature VALUE -0.3 to 7 -0.3 to 7 -20 to 65 0 to 60 UNIT V V
DC RECOMMENDED OPERATING CONDITIONS
SYMBOL Vcc ViH ViL PARAMETER Power Supply Voltage High Level Input Voltage Low Level Input Voltage MIN 3.0 2.2 -0.3 * MAX 5.5 Vcc+0.3 0.8 UNIT V V V
Note: - 0.8V (Pulse width <= 10nS)
DC CHARACTERISTICS (Ta = 0 to 65, Vcc = 3.15V to 5.5V) 0 65 SYMBOL Icco Iccs VoH VoL PARAMETER Operating Current Sleep Mode Current High Level Output Voltage Low Level Output Voltage 2.4 0.4 MIN TYP 26 75 MAX 50 200 UNIT mA uA V V
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THNCFxxxMAA Series
Physical Specifications
Preliminary version
1.60mm .05 ( .063 in .002) 3.30mm .10 ( .130 in .004 )
26
50 25 1.01mm 0.7 ( .039 in .003)
1.01mm 0.7 ( .039 in .003)
1
.99mm .05 (.039 in. . 002) 2.44mm .07 (.096 in. . 003)
2x25.78mm .07 (2X1.015 in .003)
2X12.00mm .10 (2X.472 in .004)
36.40mm .15 .006) (1.433 in.
TOP
2.15mm .07 (.085 in. . 003) 2X 3.00mm (2X .118 in. .07 . 003)
0.76mm (0.30 in.
.07 . 003)
4XR 0.5mm .1 (4XR.020 in. . 004)
41.66mm .13(1.640 in. . 005) 42.80mm .10) (1.685 in. . 004)
0.63mm .07 (.025 in. . 003)
Note: The optional notched configuration was shown in the CF Specification Rev.1.0. In Specification Rev. 1.2. the notch was removed for ease of tooling. This optional configuration can be used but it is not recommended.
Type I CompactFlash Storage Card and CF+ Card Dimensions
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THNCFxxxMAA Series
Electrical Interface
Physical Description
Preliminary version
The host is connected to the CompactFlash Storage Card or CF+ Card using a standard 50-pin connector. The connector in the host consists of two rows of 25 male contacts each on 50 mil (1.27 mm) centers.
Pin Assignments and Pin Type
The signal/pin assignments are listed in Table 4. Low active signals have a "-" prefix. Pin types are Input, Output or Input/Output. Section 4.3 defines the DC characteristics for all input and output type structures.
Electrical Description The CompactFlash Storage Card functions in three basic modes: 1) PC Card ATA using I/O Mode, 2) PC Card ATA using Memory Mode and 3) True IDE Mode, which is compatible with most disk drives. CompactFlash Storage Cards are required to support all three modes. The CF Cards normally function in the first and second modes, however they can optionally function in True IDE mode. The configuration of the CompactFlash Card will be controlled using the standard PCMCIA configuration registers starting at address 200h in the Attribute Memory space of the storage card.or for True IDE Mode, pin 9 being grounded. The configuration of the CF Card will be controlled using configuration registers. The configuration registers are starting at the address defined in the Configuration Tuple (CISTPL_CONFIG) in the Attribute Memory space of the CF Card. Signals whose source is the host are designated as inputs while signals that the CompactFlash Storage Card sources are outputs. The CompactFlash Storage Card logic levels conform to those specified in the PCMCIA Release 2.1 specification. Each signal has three possible operating modes: 1) PC Card Memory mode 2) PC Card I/O mode 3) True IDE mode
True IDE mode is required for CompactFlash Storage cards. All outputs from the card are totem pole except the data bus signals that are bi-directional tri-state.
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Pin Assignments and Pin Type
PC Card Memory Mode Pin Num. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Signal Name GND D03 D04 D05 D06 D07 -CE1 A10 -OE A09 A08 A07 VCC A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 WP -CD2 -CD1 1 D11 1 D12 1 D13 1 D14 1 D15 1 -CE2 -VS1 -IORD -IOWR -WE Pin Type I/O I/O I/O I/O I/O I I I I I I I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I In,Out Type Ground I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I3U I1Z I3U I1Z I1Z I1Z Power I1Z I1Z I1Z I1Z I1Z I1Z I1Z I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 OT3 Ground Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3U Ground I3U I3U I3U Pin Num. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PC Card I/O Mode Signal Name GND D03 D04 D05 D06 D07 -CE1 A10 -OE A09 A08 A07 VCC A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 -IOIS16 -CD2 -CD1 1 D11 1 D12 1 D13 1 D14 1 D15 1 -CE2 -VS1 -IORD -IOWR -WE Pin Type I/O I/O I/O I/O I/O I I I I I I I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I In,Out Type Ground I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I3U I1Z I3U I1Z I1Z I1Z Power I1Z I1Z I1Z I1Z I1Z I1Z I1Z I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 OT3 Ground Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I3U Ground I3U I3U I3U Pin Num. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 True IDE Mode Signal Name GND D03 D04 D05 D06 D07 -CS0 2 A10 -ATA SEL 2 A09 2 A08 2 A07 VCC 2 A06 2 A05 2 A04 2 A03 A02 A01 A00 D00 D01 D02 -IOCS16 -CD2 -CD1 1 D11 1 D12 1 D13 1 D14 1 D15 1 -CS -VS1 -IORD -IOWR 3 -WE Pin Type I/O I/O I/O I/O I/O I I I I I I I I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I In,Out Type Ground I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I3Z I1Z I3U I1Z I1Z I1Z Power I1Z I1Z I1Z I1Z I1Z I1Z I1Z I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 ON3 Ground Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z Ground I3Z I3Z I3U
Preliminary version
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Preliminary version
PC Card Memory Mode Pin Num. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name RDY/BSY VCC -CSEL -VS2 RESET -WAIT -INPACK -REG BVD2 BVD1 1 D08 1 D09 1 D10 GND Note: Pin Type O I O I O O I I/O I/O I/O I/O I/O In,Out Type OT1 POWER I2Z OPEN I2Z OT1 OT1 I3U I1U, OT1 I1U, OT1 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 Ground Pin Num. 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PC Card I/O Mode Signal Name IREQ VCC -CSEL -VS2 RESET -WAIT -INPACK -REG -SPKR -STSCHG 1 D08 1 D09 1 D10 GND Pin Type O I O I O O I I/O I/O I/O I/O I/O In,Out Type OT1 Power I2Z OPEN I2Z OT1 OT1 I3U I1U,OT1 I1U,OT1 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 Ground Pin Num. 37 38 39 40 41 42 43 44 45 46 47 48 49 50
True IDE Mode Signal Name INTRQ VCC -CSEL -VS2 -RESET IORDY -INPACK 3 -REG -DASP -PDIAG 1 D08 1 D09 1 D10 GND Pin Type O I O I O O I I/O I/O I/O I/O I/O In,Out Type OZ1 Power I2U OPEN I2Z ON1 OZ1 I3U I1U,ON1 I1U,ON1 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 Ground
1. These signals are required only for 16bit access and not required when installed in 8-bit systems. Devices should allow for 3-state signals not to consume current. 2. Should be grounded by the host. 3. Should be tied to VCC by the host. 4. Optional for CF+Cards, required for CompactFlash Storage Cards.
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THNCFxxxMAA Series
Signal Signal Description
Signal Name
A10 - A0 (PC Card Memory Mode)
Preliminary version
Dir.
I
Pin
8,10,11,12 14,15,16,17, 18,19,20
Description
These address lines along with the -REG signal are used to select the following: The I/O port address registers within the CompactFlash Storage Card or CF+Card, the memory mapped port address registers within the CompactFlash Storage Card or CF+Card, a byte in the card's information structure and its configuration control and status registers. This signal is the same as the PC Card Memory Mode signal.
A10 - A0 (PC Card I/O Mode) A2 - A0 (True IDE Mode) BVD1 (PC Card Memory Mode) -STSCHG (PC Card I/O Mode) Status Changed -PDIAG (True IDE Mode) BVD2 (PC Card Memory Mode) -SPKR (PC Card I/O Mode) -DASP (True IDE Mode) -CD1, -CD2 (PC Card Memory Mode) O 26,25 I/O 45 I 18,19,20
In True IDE Mode only A[2:0] are used to select the one of eight registers in the Task File, the remaining address lines should be grounded by the host. This signal is asserted high as BVD1 is not supported. This signal is asserted low to alert the host to changes in the RDY/-BSY and Write Protect states, while the I/O interface is configured. Its use is controlled by the Card Config and Status Register. In the True IDE Mode, this input/output is the Pass Diagnostic signal in the Master/Slave handshake protocol. This signal is asserted high as BVD2 is not supported. This line is the Binary Audio output from the card. If the Card does not support the Binary Audio function, this line should be held negated. In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in the Master/Slave handshake protocol. These Card Detect pins are connected to ground on the CompactFlash Storage Card or CF+Card. They are used by the host to determine that the CompactFlash Storage Card or CF+Card is fully inserted into its socket. This signal is the same for all modes. This signal is the same for all modes.
I/O
46
-CD1, -CD2 (PC Card I/O Mode) -CD1, -CD2 (True IDE Mode) -CE1, -CE2 (PC Card Memory Mode) Card Enable I 7,32
These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. -CE2 always accesses the odd byte of the word, -CE1accesses the even byte or the Odd byte of the word depending on A0 and -CE2. A multiplexing scheme based on A0, -CE1, -CE2 allows 8 bit hosts to access all data on D0-D7. See Tables 4-11, 4-12, 4-15, 4-16 and 4-17. This signal is the same as the PC Card Memory Mode signal. In the True IDE Mode CS0 is the chip select for the task file registers while CS2 is used to select the Alternate Status Register and the Device Control Register.
-CE1, -CE2 (PC Card I/O Mode) Card Enable -CS0, -CS1 (True IDE Mode)
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THNCFxxxMAA Series
Signal Name
-CSEL (PC Card Memory Mode) -CSEL (PC Card I/O Mode) -CSEL (True IDE Mode)
Preliminary version
Dir.
I
Pin
39
Description
This signal is not used for this mode. This signal is not used for this mode. This internally pulled up signal is used to configure this device as a Master or a Slave when configured in the True IDE Mode. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave.
D15 - D00 (PC Card Memory Mode)
I/O
31,30,29,28, 27,49,48,47, 6,5,4,3,2,23, 22,21
These lines carry the Data, Commands and Status information between the host and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB of the Odd Byte of the Word. This signal is the same as the PC Card Memory Mode signal. In True IDE Mode, all Task File operations occur in byte mode on the low order bus D00-D07 while all data transfers are 16bit using D00-D15.
D15 - D00 (PC Card I/O Mode) D15 - D00 (True IDE Mode) GND (PC Card Memory Mode) GND (PC Card I/O Mode) GND (True IDE Mode) -INPACK (PC Card Memory Mode) -INPACK (PC Card I/O Mode) Input Acknowledge O 43 1, 50
Ground This signal is the same for all modes. This signal is the same for all modes. This signal is not used in this mode. The input Acknowledge signal is asserted by the CompactFlash Storage Card or CF+ Card when the card is selected and responding to an I/O read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the CompactFlash Storage Card or CF+Card and the CPU. In True IDE mode this output signal is not used and should not be connected at the host.
-INPACK (True IDE Mode) -IORD (PC Card Memory Mode) -IORD (PC Card I/O Mode) -IORD (True IDE Mode) -IOWR (PC Card Memory Mode) -IOWR (PC Card I/O Mode) I 35 I 34
This signal is not used in this mode. This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the CompactFlash Storage Card or CF+Card when the card is configured to use the I/O interface. In True IDE Mode, this signal has the same function as in PC Card I/O Mode. This signal is not used in this mode. The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the CompactFlash Strage Card or CF+Card controller registers when the CompactFlash Storage Card or CF+Card is configured to use the I/O interface. The clocking will occur on the negative to positive edge of the signal(trailing edge).
-IOWR (True IDE Mode)
In True IDE Mode, this signal has the same function as in PC Card I/O Mode.
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Signal Name
-OE (PC Card Memory Mode) -OE (PC Card I/O Mode) -ATA SEL (True IDE Mode) RDY/-BSY (PC Card Memory Mode) O 37
Preliminary version
Dir.
I
Pin
9
Description
This is an Output Enable strobe generated by the host interface. It is used to read data from the CompactFlash Strage Card or CF+Card in Memory Mode and to read the CIS and configuration registers. In PC Card I/O Mode, this signal is used to read the CIS and configuration registers. To enable True IDE Mode this Input should be grounded by the host. In Memory Mode this signal is set high when the CompactFlash Storage Card or CF+Card is ready to accept a new data transfer operation and held low when the card is busy. The Host memory card socket must provide a pull-up resistor. At power up and at Reset, the RDY/-BSY signal is held low(busy) until the CompactFlash Storage Card or CF+Card has completed its power up or reset function. No access of any type should be made to the CompactFlash Storage Card or CF+Card during this time. The RDY/-BSY signal is held high(disabled from being busy) whenever the following condition is true: The CompactFlash Storage Card or CF+Card has been powered up with +RESET continuously disconnected or asserted.
-IREQ (PC Card I/O Mode) INTRQ (True IDE Mode) -REG (PC Card Memory Mode) Attribute Memory Select -REG (PC Card I/O Mode) -REG (True IDE Mode) RESET (PC Card Memory Mode) I 41 I 44
I/O Operation -After the CompactFlash Storage Card or CF+Card has been configured for I/O operation, this signal is used as -Interrupt Request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. In True IDE Mode signal is the active high Interrupt Request to the host. This signal is used during Memory Cycles to distinguish between Common Memory and Register (Attribute) Memory accesses. High for Common Memory, Low for Attribute Memory. The signal must also be active (low) during I/O Cycles when the I/O address is on the Bus. In True IDE Mode this input signal is not used and should be connected to VCC by the host. When the pin is high, this signal Resets the CompactFlash Storage Card or CF+Card. The CompactFlash Storage Card or CF+Card is Reset only at power up if this pin is left high or open from power-up. The CompactFlash Storage Card or CF+Card is also Reset when the Soft Reset bit in the Card Configuration Option Register is set. This signal is the same as the PC Card Memory Mode signal. In the True IDE Mode this input pin is the active low hardware reset from the host. 13,38 +5V, +3.3V power This signal is the same for all modes. This signal is the same for all modes.
RESET (PC Card I/O Mode) -RESET (True IDE Mode) VCC (PC Card Memory Mode) VCC (PC Card I/O Mode) VCC (True IDE Mode)
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Preliminary version
Signal Name
-VS1 -VS2 (PC Card Memory Mode) -VS1 -VS2 (PC Card I/O Mode) -VS1 -VS2 (True IDE Mode) -WAIT (PC Card Memory Mode) -WAIT (PC Card I/O Mode) IORDY (True IDE Mode) -WE (PC Card Memory Mode)
Dir. Pin
O 33 40
Description
Voltage Sense Signals. -VS1 is grounded so that the CompactFlash Storage Card or CF+Card CIS can be read at 3.3 volts and -VS2 is reserved by PCMCIA for a secondary voltage. This signal is the same for all modes.
This signal is the same for all modes.
O
42
The -WAIT signal is driven low by the CompactFlash Storage Card or CF+Card to signal the host to delay completion of a memory or I/O cycle that is in progress. This signal is the same as the PC Card Memory Mode signal. In True IDE Mode this output signal may be used as IORDY.
I
36
This is a signal driven by the host and used for strobing memory write data to the registers of the CompactFlash Storage Card Storage Card or CF+Card when the card is configured in the memory interfacce mode. It is also used for writing the configuration registers. In PC Card I/O Mode, this signal is used for writing the configuration registers. In True IDE Mode this input signal is not used and should be connected to VCC by the host.
-WE (PC Card I/O Mode) -WE (True IDE Mode) WP (PC Card Memory Mode) Write Protect -IOIS16 (PC Card I/O Mode) O 24
Memory Mode - The CompactFlash Storage Card or CF+Card does not have a write protect switch. This signal is held low after the completion of the reset initialization sequence. I/O Operation - When the CompactFlash Storage Card or CF+Card is configured for I/O Operation Pin 24 is used for the -I/O Selected is 16Bit Port (-IOIS16) function. A Low signal indicates that a 16bit or odd byte only operation can be performed at the addressed port. In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer cycle.
-IOIS 16 (True IDE Mode)
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THNCFxxxMAA Series
Access Specifications
1. Attribute access specifications When CIS-ROM region or Configuration register region is accessed, read and write operations are executed under the condition of -REG="L" as follows. That region can be accessed by Byte/World/Old-byte modes, which are defined by PC card standard specifications. Attribute Read Access Mode Mode Standby mode Byte access(8-bit) Word access(16-bit) Odd byte access(8-bit) Note: x: L or H Attribute Write Access Mode Mode Standby mode Byte access(8-bit) -REG x L L L L -CE2 H H H L L -CE1 H L L L H A0 x L H x x -OE x H H H H -WE x L L L L D8 to D15 Don't care Don't care Don't care Don't care Don't care D0 to D7 Don't care even byte Don't care even byte Don't care -REG x L L L L -CE2 H H H L L -CE1 H L L L H A0 x L H x x -OE x L L L L -WE x H H H H D8 to D15 High-Z High-Z High-Z invalid invalid D0 to D7 High-Z even byte invalid even byte High-Z
Preliminary version
Word access(16-bit) Odd byte access(8-bit) Note: x: L or H Note: write CIS-ROM region is invalid. Attribute Access Timing Example
A0 to A10 -REG -CE2/-CE1 -OE -WE D0 to D15
Dout
Din
read cycle
write cycle
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THNCFxxxMAA Series
Task File register access specifications There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address area. Each case of Task File registers read and write operations is executed under the condition as follows. That area can be accessed by Byte/World/Odd Byte modes, which are defined by PC card standard specifications. (1) I/O address map Task File Register Read Access Mode (1) Mode Standby mode Byte access(8-bit) Word access(16-bit) Odd byte access(8-bit) Note: x: L or H -REG x L L L L -CE2 H H H L L -CE1 H L L L H A0 -IORD -IOWR -OE -WE x x x x x L L H H H H L H H H x L H H H x L H H H D8 to D15 High-Z High-Z High-Z odd byte odd byte D0 to D7 High-Z even byte odd byte even byte High-Z
Preliminary version
Task File Register Write Access Mode (1) Mode Standby mode Byte access(8-bit) Word access(16-bit) Odd byte access(8-bit) Note: x: L or H -REG x L L L L -CE2 H H H L L -CE1 H L L L H A0 -IORD -IOWR -OE -WE x x x x x L H L H H H H L H H x H L H H x H L H H D8 to D15 Don't care Don't care Don't care odd byte odd byte D0 to D7 Don't care even byte odd byte even byte Don't care
(1 Task File Register Access Timing Example (1)
A0 to A10 -REG -CE2/-CE1 -IORD -IOWR D0 to D15 Dout Din
read cycle
write cycle
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Memory address map Task File Register Read Access Mode (2) Mode -REG -CE2 -CE1 Standby mode x H H Byte access(8-bit) H H L H H L Word access(16-bit) H L L Odd byte access(8-bit) H L H Note: x: L or H Task File Register Write Access Mode (2) Mode Standby mode Byte access(8-bit) Word access(16-bit) Odd byte access(8-bit) Note: x: L or H -REG x H H H H -CE2 H H H L L -CE1 H L L L H A0 -OE -WE -IORD -IOWR x x x x x L H L H H H H L H H x H L H H x H L H H D8 to D15 Don't care Don't care Don't care odd byte odd byte D0 to D7 Don't care even byte odd byte even byte Don't care A0 -OE -WE -IORD -IOWR x x x x x L L H H H H L H H H x L H H H x L H H H D8 to D15 High-Z High-Z High-Z odd byte odd byte D0 to D7 High-Z even byte odd byte even byte High-Z
Preliminary version
Task File Register Access Timing Example (2)
A0 to A10 -REG -CE2/-CE1 -OE -WE D0 to D15 read cycle Dout Din write cycle
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True IDE Mode The card can be configured in a True IDE This card is configured in this mode only when the-OE input signal is asserted GND by the host. In this True IDE mode Attribute Registers are not accessible from the host. Only I/O operation to the task file and data register is allowed. If this card is configured during power on sequence, data register is accessed in word (16-bit). The card permits 8-bit accessed if the user issues a Set Feature Command to put the device in 8-bit mode. True IDE Mode Read I/O Function IDE Mode -CE2 Invalid mode L Standby mode H Data register access H Alternate status access L Other task file access H Note: x: L or H True IDE Mode Write I/O Function Mode -CE2 Invalid mode L Standby mode H Data register access H Control register access L Other task file access H Note: x: L or H
Preliminary version
-CE1 L H L H L
A0 to A2 x x 0 6H 1-7H
-IORD x x L L L
-OWR x x H H H
D8 to D15 High-Z High-Z odd byte High-Z High-Z
D0 to D7 High-Z High-Z even byte status out data
-CE1 L H L H L
A0 to A2 x x 0 6H 1-7H
-IORD x x H H H
-OWR x x L L L
D8 to D15 don't care don't care odd byte don't care don't care
D0 to D7 don't care don't care even byte control in data
True IDE Mode I/O Access Timing Example
A0 to A2 -CE -IORD -IOWR -IOIS16 D0 to D15 read cycle Dout Din write cycle
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Configuration register specifications This card supports four Configuration registers for the purpose of the configuration and observation of this card. These registers can be used in memory card mode and I/O card mode. In True IDE mode, these registers can not be used. 1. Configuration Option register(Address 200H) This register is used for the configuration of the card configuration status and for the issuing soft reset to the card. bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SRESET LevlREQ INDEX Note: initial value: 00H Name SRESET R/W R/W Function Setting this bit to "1", places the card in the reset state (Card Hard Reset). This operation is equal to Hard Reset, except this bit is not cleared. Then this bit set to "0", places the card in the reset state of Hard Reset (This bit is set to "0" by Hard Reset). Card configuration status is reset and the card internal initialized operation starts when Card Hard Reset is executed, so next access to the card should be the same sequence as the power on sequence. This bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode interrupt is selected. This bits is used for select operation mode of the card as follows. When Power on, Card Hard Reset and Soft Reset, this data is "000000" for the purpose of Memory card interface recognition.
Preliminary version
LevlREQ (HOST->) INDEX (HOST->)
R/W R/W
INDEX bit assignment INDEX bit 543210 000000 000001 000010 000011
Card mode Memory card I/O card I/O card I/O card
Task File register address 0H to FH, 400H to 7FFH xx0H to xxFH 1F0H to 1F7H,3F6H to 3F7H 1F0H to 177H,376H to 3F7H
Mapping mode Memory mapped contiguous I/O mapped primary I/O mapped Secondary I/O mapped
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(Address 2. Configuration and Status register (Address 202H) This register is used for observing the state of the card. bit7 bit6 bit5 bit4 bit3 CHGED SIGCHG IOIS8 0 0 Note: initial value: 00H Name CHGED (CARD->) SIGCHG (HOST->) R/W R
Preliminary version
bit2 PWD
bit1 INTR
bit0 0
R/W
IOIS8 (HOST->) PWD (HOST->)
R/W R/W
INTR (CARD->)
R
Function This bit indicates that CRDY/-BSY bit on Pin Replacement register is set to "1". When CHGED bit is set to "1", -STSCHG pin is held "L" at the condition of SIGCHG bit set to "1" and the card configured for the I/O interface. This bit is set or reset by the host for enabling and disabling the status-change signal (-STSCHG pin). When the card is configured I/O card interface and this bit is set "1", -STSCHG pin is controlled by CHGED bit. If this bit is set to "0", -STSCHG pin is kept "H". The host sets this field to "1" when it can provide I/O cycles only with on 8 bit data bus (D7 to D0). When this bit is set to "1", the card enters sleep state (Power Down mode). When this bit is reset to "0", the card transfers to idle state (active mode). RRDY/BSY bit on Pin Replacement Register becomes BUSY when this bit is changed. RRDY/BSY will not become Ready until the power state requested has been entered. This card automatically powers down when it is idle and powers back up when it receives a command. This bit indicates the internal state of the interrupt request. This bit state is available whether I/O card interface has been configured or not. This signal remains true until the condition, which caused the interrupt request, has been serviced. If the -IEN bit in the Device Control Register disables interrupts, this bit is a zero.
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3. Pin Replacement register (Address 204H) This register is used for providing the state of -IREQ signal when the card configured I/O card interface. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 CRDY/-BSY 0 1 1 RRDY/-BSY 0 Note: initial value: 0CH Name CRDY/-BSY (HOST->) RRDY/-BSY (HOST->) R/W R/W R Function This bit is set to "1" when the RRDY/-BSY bit changes state. The host may also write this bit. When read, this bit indicates +READY pin states. When written, this bit is used for CRDY/-BSY bit masking.
Preliminary version
4. Socket and Copy register (Address 206H) This register is used for identification of the card from the other cards. Host can read and write this register. Host should set this register before this card's Configuration Option register set. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 DRV# 0 0 0 0 Note: initial value: 00H Name DRV# (HOST->) R/W R Function These fields are used for the configuration of the plural cards. When host configures the plural cards, written the card's copy number in this field. In this way, host can perform the card's master/slave organization.
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CIS information CIS information of CompactFlash card is defined as follows.
Address Data Description of contents CIS function
Preliminary version
000H 002H 004H 006H 008H 00AH 00CH 00EH 010H 012H 014H 016H 018H 01AH 01CH 01EH 020H 022H 024H 026H 028H 02AH 02CH 02EH 030H 032H 034H 036H 038H 03AH 03CH 03EH 040H 042H 044H 046H 048H 04AH 04CH
01h 03h d9h 01h ffh 1ch 04h 03h d9h 01h ffh 18h 02h dfh 01h 20h 04h 00h 00h 00h 00h 15h 20h 04h 01h xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh
CISTPL_DEVICE TPL_LINK Device information Device information END MARKER CISTPL_DEVICE_OC TPL_LINK Conditions information Device information Device information END MARKER CISTPL_JEDEC_C TPL_LINK PCMCIA's manufacture's JEDEC code PCMCIA's JEDEC device code CISTPL_MANFID TPL_LINK Low byte of manufacturer's ID code High byte of manufacturer's ID code Low byte of product code High byte of product code CISTPL_VERS_1 TPL_LINK TPLLV1_MAJOR TPLLV1_MINOR ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings)
Tuple code Tuple link Tuple data Tuple data End of Tuple Tuple code Tuple link Tuple data Tuple data Tuple data End of Tuple Tuple code Tuple link ID Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data 2001-09-05 20/52
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04EH 050H 052H 054H 056H 058H 05AH 05CH 05EH 060H 062H 064H 066H 068H 06AH 06CH 06EH 070H 072H 074H 076H 078H 07AH 07CH 07EH 080H 082H 084H 086H 088H 08AH 08CH 08EH 090H 092H 094H 096H 098H 09AH 09CH 09EH 0A0H 0A2H 0A4H xxh xxh xxh xxh xxh 00h xxh xxh xxh xxh xxh xxh xxh xxh 00h ffh 21h 02h 04h 01h 22h 02h 01h 01h 22h 03h 02h 0ch 0fh 1ah 05h 01h 03h 00h 02h 0fh 1bh 08h c0h c0h a1h 01h 55h 08h ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) Null terminator ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) ' ' (Vender Specific Strings) Null terminator END MARKER CISTPL_FUNCID TPL_LINK IC Card function code System initialization bit mask CISTPL_FUNCE TPL_LINK Type of extended data Function information CISTPL_FUNCE TPL_LINK Type of extended data Function information Function information CISTPL_CONFIG TPL_LINK Size field Index number of last entry Configuration register base address (Low) Configuration register base address (High) Configuration register present mask CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Interface Descriptor Feature Select Vcc Selection Byte Nom V Paramete Memory length (256 byte pages) Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data End of Tuple Tuple code Tuple link Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data 2001-09-05 21/52
Preliminary version
THNCFxxxMAA Series
0A6H 0A8H 0AAH 0ACH 0AEH 0B0H 0B2H 0B4H 0B6H 0B8H 0BAH 0BCH 0BEH 0C0H 0C2H 0C4H 0C6H 0C8H 0CAH 0CCH 0CEH 0D0H 0D2H 0D4H 0D6H 0D8H 0DAH 0DCH 0DEH 0E0H 0E2H 0E4H 0E6H 0E8H 0EAH 0ECH 0EEH 0F0H 0F2H 0F4H 0F6H 0F8H 0FAH 0FCH 00h 20h 1bh 06h 00h 01h 21h b5h 1eh 4dh 1bh 0ah c1h 41h 99h 01h 55h 64h f0h ffh ffh 20h 1bh 06h 01h 01h 21h b5h 1eh 4dh 1bh 0fh c2h 41h 99h 01h 55h eah 61h f0h 01h 07h f6h 03h Memory length (256 byte pages) Misc features CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Feature Select Vcc Selection Byte Nom V Parameter Nom V Parameter Peak I Parameter CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Interface Descriptor Feature Select Vcc Selection Byte Nom V Parameter I/O param IRQ parameter IRQ request mask IRQ request mask Misc features CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Feature Select Vcc Selection Byte Nom V Parameter Nom V Parameter Peak I Parameter CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Interface Descriptor Feature Select Vcc Selection Byte Nom V Parameter I/O param I/O range length and size Base address Base address Address length Base address Base address Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple date Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data 2001-09-05 22/52
Preliminary version
THNCFxxxMAA Series
0FEH 100H 102H 104H 106H 108H 10AH 10CH 10EH 110H 112H 114H 116H 118H 11AH 11CH 11EH 120H 122H 124H 126H 128H 12AH 12CH 12EH 130H 132H 134H 136H 138H 13AH 13CH 13EH 140H 142H 144H 146H 148H 14AH 01h eeh 20h 1bh 06h 02h 01h 21h b5h 1eh 4dh 1bh 0fh c3h 41h 99h 01h 55h eah 61h 70h 01h 07h 76h 03h 01h eeh 20h 1bh 06h 03h 01h 21h b5h 1eh 4dh 14h 00h ffh Address length IRQ parameter Misc features CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Feature Select Vcc Selection Byte Nom V Parameter Nom V Parameter Peak I Parameter CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Interface Descriptor Feature Select Vcc Selection Byte Nom V Parameter I/O param I/O range length and size Base address Base address Address length Base address Base address Address length IRQ parameter Misc features CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Byte Feature Select Vcc Selection Byte Nom V Parameter Nom V Parameter Peak I Parameter CISTPL_NO_LINK TPL_LINK CISTPL_END Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link Tuple data Tuple data Tuple data Tuple data Tuple data Tuple data Tuple code Tuple link End of Tuple
Preliminary version
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Task File register specification These registers are used for reading and writing the storage data in this card. These registers are mapped five types by the configuration of INDEX in Configuration Option register. The decoded addresses are shown as follows. Memory map (INDEX=0) -REG 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 A9 to A4 x x x x x x x x x x x x x x x A3 0 0 0 0 0 0 0 0 1 1 1 1 1 x x A2 0 0 0 0 1 1 1 1 0 0 1 1 1 x x A1 0 0 1 1 0 0 1 1 0 0 0 1 1 x x A0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 Offset 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H DH EH FH 8H 9H -OE=L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Dup. even data register Dup. odd data register Dup. error register Alt. status register Drive address register Even data register Odd data register -WE=L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Dup. even data register Dup. odd data register Dup. feature register Device control register Reserved Even data register Odd data register
Preliminary version
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Contiguous I/O map (INDEX=1) -REG 0 0 0 0 0 0 0 0 0 0 0 0 0 A10 to A4 x x x x x x x x x x x x x A3 0 0 0 0 0 0 0 0 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 1 0 1 Offset 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H DH EH FH -IORD=L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Dup. even data register Dup. odd data register Dup. error register Alt. status register Drive address register -IOWR=L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Dup. even data register Dup. odd data register Dup. feature register Device control register Reserved
Preliminary version
Primary I/O map (INDEX=2) -REG 0 0 0 0 0 0 0 0 0 0 A10 x x x x x x x x x x A9 to A4 1FH 1FH 1FH 1FH 1FH 1FH 1FH 1FH 3FH 3FH A3 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD=L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Alt. status register Drive address register -IOWR=L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Device control register Reserved
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Secondary I/O map (INDEX=3) -REG 0 0 0 0 0 0 0 0 0 0 A10 x x x x x x x x x x A9 to A4 17FH 17FH 17FH 17FH 17FH 17FH 17FH 17FH 37FH 37FH A3 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD=L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Alt. status register Drive address register -IOWR=L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Device control register Reserved
Preliminary version
True IDE Mode I/O map -CE2 1 1 1 1 1 1 1 1 0 0 -CE1 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 -IORD=L Data register Error register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Status register Alt. status register Drive address register -IOWR=L Data register Feature register Sector count register Sector number register Cylinder low register Cylinder high register Drive head register Command register Device control register Reserved
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1.Data register: This register is a 16-bit register that has read/write ability, and it is used for transferring 1 sector data between the card and the host. This register can be accessed in word mode and byte mode. This register overlaps the Error or Feature register.
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Preliminary version
D0 to D15 2.Error register: This register is a read only register, and it is used for analyzing the error content at the card accessing. This register is valid when the BSY bit in Status register and Alternate Status register are set to "0"(Ready). bit1 bit5 bit4 bit3 bit2 bit0 bit7 bit6 BBK UNC "0" IDNF "0" ABRT "0" AMNF bit Name 7 BBK(Bad Block detected) 6 UNC(Data ECC error) 4 2 0
IDNF(ID Not Found) ABRT(ABoRTed command) AMNF(Address Mark Not Found)
Function
This bit is set when a Bad Block is detected in requester ID field. This bit is set when Uncorrectable error is occurred at reading the card. The requested sector ID is in error or cannot be found. This bit is set if the command has been aborted because of the card status condition.(Not ready, Write fault, Invalid command, etc.) This bit is set in case of a general error.
3.Feature register: This register is write-only register, and provides information regarding features of the drive that the host wishes to utilize. bit1 bit5 bit4 bit3 bit2 bit0 bit7 bit6 Feature byte 5. Sector count register: This register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the card. If the value of this register is zero, a count of 256 sectors is specified. In plural sector transfer, if not successfully completed, the register contains the number of sectors, which need to be transferred in order to complete, the request. bit7 bit6
bit5 bit4 bit3 bit2 bit1 bit0
Sector count byte
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5.Sector number register: This register contains the starting sector number, which is started by following sector transfer command. bit1 bit5 bit4 bit3 bit2 bit0 bit7 bit6 Sector number byte 6.Cylinder low register: This register contains the low 8-bit of the starting cylinder address, which is started by following sector transfer command. bit1 bit5 bit4 bit3 bit2 bit0 bit7 bit6 Cylinder low byte 7.Cylinder high register: This register contains the high 8-bit of the starting cylinder address, which is started by following sector transfer command. bit1 bit5 bit4 bit3 bit2 bit0 bit7 bit6 Cylinder high byte 8.Drive head register: This register is used for selecting the Drive number and Head number for the following command. bit1 bit5 bit4 bit3 bit2 bit0 bit7 bit6 1 LBA 1 DRV Head number bit Name 71 6 LBA Function This bit is set to "1". LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address (LBA) mode. When LBA =0, CHS mode is selected. When LBA=1, LBA mode is selected. In LBA mode, the Logical Block Address is interrupted as follows: LBA07-LBA00Sector Number Register D7-D0. LBA15-LBA08Cylinder Low Register D7-D0. LBA23-LBA16Cylinder High Register D7-D0. LBA27-LBA24Drive / Head Register bits HS3-HS0. This bit is set to "1". This bit is used for selecting the Master (Card 0)and Slave(Card 1) in Master/Slave organization. The card is set to be Card 0 or 1 by using DRV# of the Socket and Copy register. This bit is used for selecting the Head number for the following command. Bit 3 is MSB.
Preliminary version
5 4
1 DRV(DriVe select)
3
Head number
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9.Status register: This register is read only register, and it indicates the card status of command execution. When this register is read in configured I/O card mode (INDEX=1,2,3) and level interrupt mode, -IREQ is negated. bit7 BSY bit6 DRDY
bit5 bit4 bit3 bit2 bit1 bit0
Preliminary version
DWF
DSC
DRQ
CORR
IDX
ERR
bit Name 7 BSY(BuSY) 6
DRVY(Drive ReaDY)
Function
This bit is set when the card internal operation is executing. When this bit is set to "1", other bits in this register are invalid. If this bit and DSC bit are set to "1", the card is capable of receiving the read or write or seek requests. If this bit is set to "0", the card prohibits these requests. This bit is set if this card indicates the write fault status. This bit is set when the drive seeks complete. This bit is set when the information can be transferred between the host and Data register. This bit is cleared when the card receives the other command. This bit is set when a correctable data error has been occurred and the data has been corrected. This bit is always set to "0". This bit is set when the previous command has ended in some type of error. The error information is set in this error register or other Status registers. This bit is cleared by the next command.
5 4 3
DWF(Drive Write Fault) DSC(Drive Seek Complete) DRQ(Data ReQuest)
2 1 0
CORR(CORRected data) IDX(InDeX) ERR(ERRor)
10.Alternate status register: This register is the same as Status register in physically, so the bit assignment refers to previous item of Status register. But this register is different from Status register that -IREQ is not negated when data read. 11.Command register: This register is write only register, and it is used for writing the command to execute the requested operation. The command codes is written in the command register, after the parameter is written in the Task File when the card is in Ready state.
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Used parameter FR SC SN N N N N N N N Y Y N Y N N N N N Y N N N N N Y N N N N N Y Y N N Y N Y Y N Y Y N N N N N N N N Y Y N N N Y N N N N N N N N N N N Y Y N N N N N N N N Y N Y Y N Y Y N Y Y N Y Y N Y Y
Preliminary version
Command Check power mode Execute drive diagnostic Erase sector Format track Identify Drive Idle Idle immediate Initialize drive parameters Read buffer Read multiple Read long sector Read sector Read verify sector Recalibrate Request sense Seek Set features Set multiple mode Set sleep mode Stand by Stand by immediate Translate sector Wear level Write buffer Write long sector Write multiple Write multiple w/o erase Write sector Write sector w/o erase Write verify
Command code E5H or 98H 90H C0H 50H ECH E3H or 97H E1H or 95H 91H E4H C4H 22H or 23H 20H or 21H 40H or 41H 1XH 03H 7XH EFH C6H E6H or 99H E2H or 96H E0H or 94H 87H F5H E8H 32H or 33H C5H CDH 30H or 31H 38H 3CH
CY N N Y Y N N N N N Y Y Y Y N N Y N N N N N Y N N Y Y Y Y Y Y
DR Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
HD N N Y Y N N N Y N Y Y Y Y N N Y N N N N N Y Y N Y Y Y Y Y Y
LBA N N Y Y N N N N N Y Y Y Y N N Y N N N N N Y N N Y Y Y Y Y Y
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Note: FR: Feature register SC: Sector Count register SN: Sector Number register CY: Cylinder register DR: DRV bit of Drive Head register HD: Head Number of Drive Head register LBA: Logical Block Address Mode Supported Y: The register contains a valid parameter for this command N: The register does not contain a valid parameter for this command 12. Device control register: This register is write only register, and it is used for controlling the card interrupt request and issuing an ATA soft reset to the card. bit7 x bit 7to 4 3 2 bit6 x Name
X 1 SRST(Software ReSeT) bit5 bit4 bit3 bit2 bit1 bit0
Preliminary version
x
x Function
1
SRST
nIEN
0
1 0
nIEN(Interrupt Enable) 0
don't care This bit is set to "1". This bit is set to "1" in order to force the card to perform Task File Reset operation. This does not change the Card Configuration registers as a Hardware Reset does. The card remains in Reset until this bit is reset to "0". This bit is used for enabling -IREQ. When this bit is set to "0", -IREQ is enabled. When this bit is set to "1", -IREQ is disabled. This bit is set to "0".
13.Drive Address register: This register is read only register, and it is used for confirming the drive status. This register is provides for compatibility with the AT disk drive interface. It is recommended that this register is not mapped into the host's I/O space because of potential conflicts on bit7. bit7 x bit 7 6 5 to 2 1 0 bit6 nWTG Name
X nWTG(WriTing Gate) nHS3-0(Head Select3-0) nDS1(Idrive Select1) nDS0(Idrive Select0) bit5 bit4 bit3 bit2 bit1 bit0
nHS3
nHS2 Function
nHS1
nHS0
nDS1
nDS0
This bit is unknown. This bit is unknown. These bits is the negative value of Head Select bits(bit 3 to 0)in Drive/Head register. This bit is unknown. This bit is unknown.
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ATA Command specifications This table summarizes the ATA command set with the paragraphs. Following shows the supported commands and command codes, which are written in command registers. ATA Command Set No. Command set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Check power mode Execute drive diagnostic Erase sector(s) Format track Identify Drive Idle Idle immediate Initialize drive parameters Read buffer Read multiple Read long sector Read sector(s) Read verify sector(s) Recalibrate Request sense Seek Set features Set multiple mode Set sleep mode Stand by Stand by immediate Translate sector Wear level Write buffer Write long sector Write multiple Write multiple w/o erase Write sector Write sector w/o erase Write verify Code E5H or 98H 90H C0H 50H ECH E3H or 97H E1H or 95H 91H E4H C4H 22H,23H 20H,21H 40H, 41H 1XH 03H 7XH EFH C6H E6H or 99H E2H or 96H E0H or 94H 87H F5H E8H 32H or 33H C5H CDH 30H or 31H 38H 3CH FR Y SC Y Y Y Y Y Y Y Y Y Y Y Y Y Y SN Y Y Y Y Y Y Y Y Y Y Y Y Y CY Y Y Y Y Y Y Y Y Y Y Y Y Y Y DR Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y HD Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y LSB Y Y Y Y Y Y Y Y Y Y Y Y Y Y
Preliminary version
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Note FRFeature Register SCSector Count register (00H to FFH) SNSector Number register (01H to 20H) CYCylinder Low/High register DRDrive bit of Drive/Head register HDHead No.(0 to 3) of Drive/Head register YSet up Not set up 1. Check Power Mode (code: E5H or 98H): This command checks the power mode. 2. Execute Drive Diagnostic (code: 90H): This command performs the internal diagnostic tests implemented by the Card. 3. Erase Sector(s)(code: C0H): This command is used to erase data sectors. 4. Format Track (code: 50H): This command writes the desired head and cylinder of the selected drive with a vendor unique data pattern (typically FFH or 00H). To remain host backward compatible, the card expects one sector (512Bytes) of data from the host to follow the command with same protocol as the Write Sector Command. 5. Identify Drive (code: ECH): This command enables the host to receive parameter information from the Card.
Preliminary version
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Identify Drive Information Word address 0 1 2 3 4 5 6 7 to 8 9 10 to 19 20 21 22 23 to 46 47 48 49 50 51 52 53 to 58 59 60 to 61 62 to 255 Default value Total bytes Data field type information 848AH XXXX 0000H 00XXH 0000H XXXX XXXX XXXX 0000H XXXX 0001H 0004H 0004H XXXX 0001H 0000H 0200H 0000H 0200H 0000H XXXX 0101H XXXX 0000H 2 2 2 2 2 2 2 4 2 20 2 2 2 48 2 2 2 2 2 2 12 2 4 388 General configuration bit-significant information Default number of cylinders Reserved Default number of heads Number of unformatted bytes per track Number of unformatted bytes per sector Default number of sectors per track Number of sectors per card(Word7=MSW,Words=LSW) Reserved Serial number in ASCII Buffer type(single ported) Buffer size in 512 byte increments # of ECC bytes passed on Read/Write Long Commands Firmware revision in ASCII etc. Maximum of 1 sector on Read/Write Multiple command Double Word not supported Capabilities: DMA NOT Supported(bit 8), LBA supported (bi 9) Reserved PIO data transfer cycle timing mode 2 DMA data transfer cycle timing mode not Supported Reserved Multiple sector setting is valid Total number of sectors addressable in LBA Mode Reserved
Preliminary version
6. Idle (code: E3H or 97H): This command causes the Card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If sector count is non-zero, the automatic power down mode is enabled. If the sector count is zero, the automatic power mode is disabled. 7. Idle Immediate (code: E1H or 95H): This command causes the Card to set BSY, enter the Idle(Read) mode, clear BSY and generate an interrupt. 8. Initialize Drive Parameters (code: 91H): This command enables the host to set the number of sectors per track and the number of heads per cylinder. 9. Read Buffer (code: E4H): This command enables the host to read the current contents of the card's sector buffer.
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10. Read Multiple (code: C4H): This command performs similarly to the Read Sectors command. Interrupts are not generated on each sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command. 11. Read Long Sector (code 22H or 23H): This command performs similarly to the Read Sector(s) command except that it returns 516 bytes of data instead of 512 bytes. 12. Read Sector(s) (code 20H, 21H): This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer beings specified in the Sector Number register. 13. Read Verify Sector(s) (code: 40H or 41H): This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the host. 14. Recalibrate (code: 1XH): This command is effectively a NOP command to the Card and is provided for compatibility purposes. 15. Request Sense (code: 03H): This command requests an extended error code after command ends with an error. 16. Seek (code: 7XH): This command is effectively a NOP command to the Card although it does perform a range check. 17. Set Features (code: EFH): This command is used by the host to establish or select certain features. Feature 01H 55H 66H 81H BBH CCH Operation Enable 8-bit data transfers. Disable Read Look Ahead. Disable Power on Reset (POR) establishment of defaults at Soft Reset. Disable 8-bit data transfers. 4 bytes of data apply on Read/Write Long commands. Enable Power on Reset (POR) establishment of defaults at Soft Reset.
Preliminary version
18. Set Multiple Mode (code: C6H): This command enables the Card to perform Read and Write Multiple operations and establishes the block count for these commands. 19. Set Sleep Mode (code: E6H or 99H): This command causes the Card to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. 20. Stand By (code: E2H or 96H): This command causes the Card to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. 21. Stand By Immediate (code: E0H or 94H): This command causes the Card to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. 22. Translate Sector (code: 87H): This command allows the host a method of determining the exact number of times a use sector has been erased and programmed.
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23. Wear Level (code: F5H): This command effectively a NOP command and only implemented for backward compatibility. The Sector Count Register will always be returned with a 00H indicating Wear Level is not needed. 24. Write Buffer (code: E8H): This command enables the host to overwrite contents of the Card's sector buffer with any data pattern desired. 25. Write Long Sector (code: 32H or 33H): This command is provided for compatibility purposes and is similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes. 26. Write Multiple (code: C5H): This command is similar to the Write Sectors command. Interrupts are not presented on each sector, but on the transfer of a block which contains the number of sectors defined by Set Multiple command. 27. Write Multiple without Erase (code: CDH): This command is similar to the Write Multiple command with the exception that an implied erase before write operation is not performed. 28. Write Sector(s): (code: 30H or 31H): This command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. 29. Write Sector(s) without Erase (code: 38H): This command is similar to the Write Sector(s) command with the exception that an implied erase before write operation is not performed. 30. Write Verify (code: 3CH): This command is similar to the Write Sector(s) command, except each sector is verified immediately after being written.
Preliminary version
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THNCFxxxMAA Series
Sector Transfer Protocol 1.Sector read: sector read procedure after the card configured I/O interface is shown as follows. Start I/O Access, INDEX=1 Set the cylinder low/high register
Preliminary version
Set the head No. of drive head register (1)Set the logical sector number Set the sector number register
Set in sector count register
Set "2H" in Command register
(2)set read sector command
N N "51H"?
Read the status register (3)Polling until ready "58H"? Y Read 256 times the data register (512 bytes)
Y
(4)Burst data transfer
error handle Get all data? Y Wait the command input
N
(5)Read more sectors?
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2.Sector write: write sector procedure after the card configured I/O interface is shown as follows.
(1)
A0 to A10 -CE1 -CE2 -IOWR -IORD D0 to D15 -IREQ 01H20H D0H 58H (Data transfer) D0H 50H
Preliminary version
(2)
7H
(3)
7H 0H
(4)
0H 7H
(5)
7H
4H 5H 6H 3H 2H 7H
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Start I/O Access, INDEX=1 Set the cylinder low/high register
Preliminary version
Set the head No. of drive head register (1)Set the logical sector number Set the sector number register
Set in sector count register
Set "30H" in command register
(2)
N N "51H"
Read the status register (3) "58H"? Y Read 256 times the data register (512 bytes)
(4)Burst data transfer
all data write Y N Y Read the status register N "51H" Y error handle "50H"? Y Wait the command input
N
(5)
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(1) A0 to A10 -CE1 -CE2 -IOWR -IORD D0 to D15 -IREQ 01H30H D0H 58H (Data transfer) D0H 50H (2) 7H
Preliminary version
(3) 7H 0H
(4) 0H 7H
(5) 7H
4H 5H 6H 3H 2H 7H
Absolute Maximum Ratings
Parameter Symbol Value Unit V V C C Note 1 All input/output voltages Vin, Vout -0.3 to VCC +0.3 VCC voltage VCC -0.3 to +6.7 Operation temperature range Topr 0 to +85 Storage temperature range Tstg -55 to +125 Note: 1. Vin, Vout min=-2.0 V for pulse width 20ns.
Recommended Operation Conditions
Parameter Operation temperature VCC voltage Symbol Ta VCC Min 0 4.5 3.15 Typ 25 5.0 3.3 Max 60 5.5 3.45 Unit C V V
(Ta=25C, Capacitance (Ta=25 C, f=1MHz)
Parameter Symbol Min Typ Max Unit pF pF Test conditions Vin=0V Vout=0V Note 1 1 Input capacitance Cin 15 Output capacitance Count 15 Note: 1. This parameter is sampled and not 100% tested.
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THNCFxxxMAA Series Card System performance
Item Set up times (Reset to ready) Set up times (Sleep to idle) Set up times (Deep power down to idle) Data transfer rate to/from host Sustained read transfer rate Sustained write transfer rate Controller overhead (Command to DRQ) Data transfer cycle end to ready(Sector write) Performance 500 ms (max) 100 s (max) 4 ms (max) 16 Mbyte/s burst (max), theoretically 5.4Mbyte/s (max), actually 3.2Mbyte/s (max), actually 4 ms (max) 500s (typ), 50 ms (max)
Preliminary version
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THNCFxxxMAA Series CharacteristicsDC Characteristics-1 (Ta=0 to +70C, VCC = 3.3V5%, 5V10%)
Parameter Parameter Input voltage Symbol VIH VIL Schmitt circuit VT+ VTOutput voltage (4mA) VOH VOL Input leakage current ILI Output leakage current ILO Pull-up current (Resistivity) IPU Pull-down current (Resistivity) IPD Sleep/standby current ISP1 Sector read current Min Typ Max Unit Test conditions 2.0 VCC+0.3 V -0.3 0.6 V 2.1 V VCC=3.3V 1.2 V 2.4 V IOH=-4mA 0.4 V IOL=4mA 1 A 1 A VOUT=high impedance 20/(165) 45/(73) 72/(45) A(k) VForce=3.3V -20/(1800) -48/(206) -72/(85) A(k) VForce=0V (0.2) (0.5) MA CMOS level (control signal=VCC-0.2) ICCR(DC) (25) (50) MA CMOS level (control signal=VCC-0.2) ICCR(Peak) (50) (80) MA ICCW(DC) (25) (50) MA CMOS level (control signal=VCC-0.2) ICCW(Peak) (50) (80) MA
Preliminary version
Sector write current
XIN
Tclkl Symbol Tclkl Tclkh
Tclkh Min 20 20 Max
Parameter clock LOW time clock HIGH time
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THNCFxxxMAA Series +6 C, 5V10%, 3.3V5%) AC Characteristics (Ta=0 to +60C, VCC = 5V 10%, VCC = 3.3V 5%)
Attribute Memory Read AC Characteristics Parameter Read cycle time Address access time -CE access time -OE access time Output disable time(-CE) Output disable time(-OE) Output enable time(-CE) Output enable time(-OE) Data valid time(A) Address setup time Symbol Tcr ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) ten(CE) ten(OE) tv(A) tsu(A) Min 100 5 5 0 30 Typ Max 100 100 50 40 40 Unit ns ns ns ns ns ns ns ns ns ns
Preliminary version
Attribute Memory Read Timing
tc ( R ) An -REG tsu ( A ) -CE ten ( CE ) -OE ten ( OE ) Dout ta ( OE ) tdls ( OE ) ta ( CE ) tdls ( CE ) ta ( A ) tv ( A )
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Attribute Memory Write AC Characteristics Parameter Write cycle time Write pulse time Address setup time Data setup time (-WE) Data hold time Write recover time Symbol tCW tw(WE) tsu(A) tsu(D-WEH) th(D) trec(WE) Min 100 60 30 40 30 20 Typ Max Unit ns ns ns ns ns ns
Preliminary version
Attribute Memory Write Timing
tc(W) -Reg An
tsu(A)
-WE
trec(WE) tw(WE) tsu(D-WEH) th(D)
-CE -OE
Din
Data in Valid
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THNCFxxxMAA Series
I/O Access Read AC Characteristics Parameter Data delay after -IORD Data hold following -IORD -IORD pulse width Address setup before -IORD Address hold following -IORD -CE setup before -IORD -CE hold following -IORD -REG setup before -IORD -REG hold following -IORD -INPACK delay failing from -IORD -INPACK delay rising from -IORD -IOIS16 delay falling from address -IOIS16 delay rising from address Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tsuREG(IORD) thREG(IORD) tdfINPACK(IORD) tdrINPACK(IORD) tdfIOIS16(ADR) tdrIOIS16(ADR) Min 0 80 30 20 0 0 0 0 0 Typ Max 45 45 45 35 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Preliminary version
Timing+ I/O Access Read Timing+
An tsuA(IORD) tsuREG(IORD) -REG tsuCE(IORD) -CE -IORD tdfINPACK(IORD) -INPACK td(IORD) -IOIS16 tdfIOIS16(ADR) Dout tdnINPACK(IORD) tdnIOIS16(ADR) tw(IORD) thA(IORD) thREG(IORD) thCE(IORD)
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I/O Access Write AC Characteristics Parameter Data setup before -IOWR Data hold following -IOWR -IOWR pulse width Address setup before -IOWR Address hold following -IOWR -CE setup before -IOWR -CE hold following -IOWR -REG setup before -IOWR -REG hold following -IOWR -IOIS16 delay falling from address -IOIS16 delay rising from address Symbol tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tsuREG(IOWR) thREG(IOWR) tdfIOIS16(ADR) tdrIOIS16(ADR) Min 40 30 80 30 20 0 0 0 0 Typ Max 35 35 Unit ns ns ns ns ns ns ns ns ns ns ns
Preliminary version
I/O Access Write Timing
An
tsuA(IOWR) tsuREG(IOWR) -REG tsuCE(IOWR)
-CE -IOWR -IOIS16
thA(IOWR) thREG(IOWR) thCE(IOWR)
th(IOWR)
tw(IOWR) tsu(IOWR) tdfIOIS16(ADR) tdrIOIS16(ADR)
Din
Din Valid
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Command Memory Access Read AC Characteristics Parameter -OE access time Output disable time (-OE) Address setup time Address hold time -CE setup time -CE hold time Symbol ta(OE) tdis(OE) tsu(A) th(A) tsu(CE) th(CE) Min 30 20 0 0 Typ Max 60 40 Unit ns ns ns ns ns ns
Preliminary version
Common Memory Access Read Timing
An tsu(A) -REG -CE -OE tdis(OE) Dout tsu(CE) ta(OE) th(CE) th(A)
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Common Memory Access Write AC Characteristic Parameter Parameter Data setup time (-WE) Data hold time Write pulse time Address setup time -CE setup time Write recover time -CE hold following -WE Symbol tsu(D-WEH) th(D) tw(WE) tsu(A) tsu(CE) trec(WE) th(CE) Min 40 30 80 30 0 20 0 Typ Max Unit ns ns ns ns ns ns ns
Preliminary version
Common Memory Access Write Timing
An tsu(A) -REG -CE -WE th(D) Din Din Valid tsu(CE) tw(WE) th(CE) trec(WE) th(A)
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The IDE Mode Access Read AC Characteristics Parameter Data delay after IORD Data hold following IORD IORD with time Address setup before IORD Address hold following IORD CE setup before IORD CE hold following IORD IOIS16 delay falling from address IOIS16 delay rising from address Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tdfIOIS16(ADR) tsfIOIS16(ADR) Min 0 80 30 20 0 0 Typ Max 45 35 35 Unit ns ns ns ns ns ns ns ns ns
Preliminary version
True IDE Mode Access Read Timing
An -CE -IORD -IOIS16
tdfIOIS16(ADR) tsuA(IORD) tsuCE(IORD) tw(IORD) tdrIOIS16(ADR) td(IORD) th(IORD) thA(IORD) thCE(IORD)
Dout
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Characteristics True IDE Mode Access Write AC Characteristics Parameter Data setup before IOWR Data hold following IOWR IORD width time Address setup before IOWR Address hold following IOWR CE setup before IOWR CE hold following IOWR IOIS16 delay falling from address IOIS16 delay rising from address Symbol tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tdfIOIS16(ADR) tsfIOIS16(ADR) Min 40 30 80 30 20 0 0 Typ Max 35 35 Unit ns ns ns ns ns ns ns ns ns
Preliminary version
True IDE Mode Access Write Timing
An -CE -IORD -IOIS16
tdfIOIS16(ADR) tsu(IOWR) Din Valid th(IOWR) tsuA(IOWR) tsuCE(IOWR) tw(IOWR) tdrIOIS16(ADR) thA(IOWR) thCE(IOWR)
Dout
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Reset Characteristics (only Memory Card Mode or I/O Card Mode) Hard Reset Characteristics Parameter Reset setup time -CE recover time VCC rising up time VCC falling down time Reset pulse width Symbol tsu(RESET) trec(VCC) tpr tpf tw(RESET) th(Hi-ZRESET) ts(Hi-ZRESET) Min 100 1 0.1 3 10 1 0 Typ Max 100 300 Unit ms s ms ms s ms ms Test conditions
Preliminary version
Hard Reset Timing
tpr 90% Vcc 10% 90% trec(Vcc) 10% tpr
-CE1, -CE2 th(Hi-ZRESET) tsu(RESET) tw(RESET) RESET High-Z Low ts(Hi-ZRESET) High-Z
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Power on Reset Characteristics Power on reset sequence must need by -PORST at the rising of VCC. Parameter -CE setup time VCC rising up time Power on Reset Timing
tpr
Preliminary version
Symbol tsu(VCC) tpr
Min 100 0.1
Typ
Max 100
Unit ms ms
Test conditions
Vcc
-PORST -CE1, -CE2
tsu(Vcc)
Attention for Card Use
In the reset or power off, the information of all registers is cleared. Notice that the card insertion/removal should not be executed during host is active, if the card is used in True IDE mode. l After the card hard reset, soft reset, or power on reset, ATA reset, command applied the card cannot access during +RDY/-BSY pin is "low" level. Flash card can't be operated in this case. l Before the card insertion VCC can not be supplied to the card. After confirmation that -CD1, -CD2 pins are inserted, supply VCC to the card. Note: -OE must be kept at the VCC level during power on reset in memory card mode and I/O card mode. -OE must be kept constantly at the GND level in True IDE mode.
l l
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